1. Field of the Invention
The present invention relates to a DMA control system enabling flyby transfer between synchronous memory such as SDRAM (synchronous dynamic random access memory) and an external device.
2. Description of the Related Art
A microprocessor contains a CPU core, and a direct memory access controller (DMAC) internally; the DMAC controls access. to an externally connected memory. For example, data transfer between the external memory and an external device is performed in that data stored in external memory is read and transferred to the external device, or data is read from the external device and transferred to the external memory.
In a typical method for such data transfer, data is read from the external memory, the read data is stored temporarily in an internal buffer of the microprocessor, and then the data stored in the internal buffer is transferred to the external device. Further, a data reading request is made to the external device, the read data is stored temporarily in the internal buffer, and then that data is written to the external memory.
FIG. 1 is a diagram showing the relationship between the microprocessor containing the DMAC, the external memory, and the external device. The microprocessor 10 is connected via a universal bus 22 to synchronous memory (SDRAM) 24 and an external device control unit 26. The external device control unit 26 includes an input/output memory 28 and controls access to the external device 30 such as a hard disk or communications device, or the like. The microprocessor 10 includes a CPU core 14, DMAC 16, and an I/O memory interface 18 for controlling the input/output memory 28, and an SDRAM interface 14 for controlling the SDRAM 24. These are each connected via the internal bus 12. Also, the microprocessor 10 includes an I/O internal buffer memory 20 for temporarily storing the data read from the I/O memory 28 in the external device control unit 26, and an SDRAM internal buffer 16 for temporarily storing data read from the SDRAM 24.
The CPU core 14 in the microprocessor 10 sends data transfer requests to the DMAC, first to read data from the SDRAM 24, which is the external memory, and supply the data to the external device 30, and secondly to take data from the external device 30 and write the data to the external memory SDRAM 24.
In the abovementioned first case, the DMAC 16 issues a read command to the SDRAM interface 14; the SDRAM interface 14 reads data by supplying the read command to the SDRAM 24, and stores the data temporarily in the SDRAM internal buffer 16. Thereafter, DMAC 16 issues an I/O write command to the I/O memory interface 18. The I/O memory interface 18 supplies the write command to I/O memory 28 and writes the data stored in the SDRAM internal buffer 16.
In the abovementioned second case, conversely, the DMAC 16 causes the I/O memory interface 18 to execute an I/O read, reads data in the I/O memory 28, and stores the data temporarily in the I/O internal buffer 20. Thereafter, a write command is supplied from the SDRAM interface 14 to the SDRAM 24 and the stored data is thus written thereto.
Consequently, for data transfer between SDRAM 24 which is the external memory and the I/O memory 28, operations to access each memory are necessary; a total of two access operation cycles are required. Moreover, this causes the system processing to become less efficient because the universal bus 22 is monopolized in each of the operation cycles.
Flyby transfer between the I/O memory 28 of the external device 30 and the SDRAM 24 is desirable. In flyby transfer, data is transferred between the device 24 and 28 directly via the universal bus 22. However, although the external device 30 can control the data effective period to a certain extent by asserting read/write commands, the cycle wherein the input/output data is effective in synchronous memory such as SDRAM is only one cycle at a predetermined timing within the command cycle because of the high-speed operations of the memory. It is therefore difficult to control data transfer through conforming to that input/output data effective cycle.
It is an object of the present invention to provide a DMA control system which enables flyby transfer for directly transferring data between a synchronous memory and an I/O memory of an external device.
In order to achieve the abovementioned object, a first aspect of the present invention is a direct memory access control system including: a direct memory access controller for issuing a flyby transfer command; a memory interface for receiving the flyby transfer command and supplying a first access command to an external synchronous memory; and an input/output interface for supplying a second access command to an external input/output memory. The input/output interface supplies a first status-signal indicating a writable timing or a read data effective timing of the input/output memory to the memory interface. The memory interface supplies a second status signal, that indicates a read data effective timing or a writable timing corresponding to the access command supplied to the synchronous memory, to the input/output interface. Until the later of the timings indicated by the first and second status signals, the memory interface and the input/output interface maintain a read data effective state and a writable state respectively.
According to the abovementioned invention, while supplying the respective status signals indicating timings of the read data effective state or writable state between the input/output interface and memory interface, both interfaces maintain the read data effective state and writable state of the input/output memory and synchronous memory under control until the later timing comes up. Consequently, it is possible to match the read data effective timing and writable timing of the synchronous memory and input/output memory, thus making possible flyby transfer of data between both memories.
In a preferred embodiment of the abovementioned invention, the memory interface extends the read data effective state by negating a clock enable signal for controlling a clock input to the synchronous memory. In effect, the memory interface extends the read data effective state by maintaining the state of negating the clock enable signal until the timing of the first status signal. Also, the memory interface supplies a write command, for instructing writing to the synchronous memory, to the synchronous memory in accordance with the timing of the first status signal.
In a preferred embodiment of the abovementioned invention, the input/output interface maintains the state of asserting the read signal to the input/output memory until the timing of the second status signal. Also, the input/output interface maintains the state of asserting the write signal to the input/output memory until the timing of the second status signal.
Furthermore, in a preferred embodiment of the abovementioned invention, the input/output interface counts the access cycles to the external device under control and outputs the first status signal when the count ends, or supplies the count value to the memory interface. Or, the input/output interface outputs the first status signal in response to a ready signal from the external device under control.
Furthermore, in a preferred embodiment of the abovementioned invention, the memory interface counts the number of cycles, until the read data effective state or the writable state, of the synchronous memory under control and outputs the second status signal when that count ends, or supplies the count value to the input/output memory interface.
Furthermore, in a preferred embodiment of the abovementioned invention, at a time of burst transfer for successively transferring data, the memory interface negates a clock enable signal for controlling clock input to the synchronous memory to maintain a state of completed setup for data input/output, and asserts the clock enable signal at the timing of the first status signal, to initiate the next input/output setup.